SginalTap: Some nodes not listed in NodeFinder?!

I somehow have the feeling, that SignalTap doesnt notice the updates in my design. If for example, I change the instance name of my module, the node finder still displays the signal names with the old module name?!

Is there anything like a refresh in SignalTap?

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I am using SignalTap to monitor the runtime-signals of my verilog design. However, I just have the situation, that after compiling the whole design in Quartus and when I want to add signals to SignalTap setup for monitoring, that using the SignalTap: pre-synthesis filter for some weird reasons some registers are enlisted, but some are not?!

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The nodes are probably still there, the names are just not present at the level of the hierarchy you want to probe at. You can add synthesis 'keep' and 'preserve' attributes to signals, eg.,

	// PLL locked
	// (the synthesis attributes allow SignalTap II use)
	logic		 pll_locked_raw       /* synthesis keep */;
	logic		 pll_locked_filtered  /* synthesis keep */;

Then resynthesize the design, open SignalTap, and add these pre-synthesis nodes (yeah, I know, all presynthesis nodes should really be listed, but they aren't).

Cheers,

Dave

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Thanks for your answer, I will try this right after this post. But a quick questino before that... why are some other registers in the very same design present in SignalTap?

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*All* of the registers are probably still there, however, the name of the signal you want to probe just doesn't happen to exist at the level you want. For example, lets say I have an FSM signal I call 'enable', and then at a higher level of the hierarchy its called 'rx_pll_enable'. I might want to probe the signal called 'rx_pll_enable', but what Quartus preserves is the 'enable' name down at the level of the FSM, since that is where the driving register is located. By adding the synthesis attribute, you can keep the name you want to probe.

Its a pain, since you often have to re-synthesize the design a couple of times before you get all the synthesis attributes right, but it does work ... :)

Cheers,

Dave

Ok, I understand, thanks for your explanation.

But somehow it still doesnt work, even with /* synthesis preserve */ (for my register).

I think it is something really weird: I reduced the whole design to only a few registers now, which are displayed in SignalTap after compilation. Let's say one of these signal is called read_base. Ok, but there is a register called r_res, which is not displayed. So what I tried now, is replacing each occurence of 'read_base' with 'r_res', simply changing the name, nothing else. And also, having the synthesis preserve attribute declared next to this register.

However if I now recompile the design and try to add the nodes, read_base disappeared now, okay. But there is no r_res listed in the node finder whatsoever.

How can this be?

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How can this be?

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Its hard to say. There are several synthesis attributes - you could try a couple of others to see if it makes any difference.

If you're at the top-level of the design, you can always route the signal to an I/O pin. This may force Quartus to eliminate some optimizations - you don't have to probe the I/O pins, you still use SignalTap - its just a way to try and figure out what is going on.

Cheers,

Dave

YES!

Thank you so so much! The noprune attribute is what I needed!

But isnt it a bug, this behaviour? As mentioned before, pre-synthesis should save all nodes, no?

-.- Costing me 6 hours of my life.

But thank you so much again, Dave!

Jimmy

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Thank you so so much! The noprune attribute is what I needed!

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Now that you mention it, I think that is the one that I had to use. If I recall correctly, you need this one if the register does not feed any real logic.

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But isnt it a bug, this behaviour? As mentioned before, pre-synthesis should save all nodes, no?

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I'm not sure its a bug, its just the way it has always worked. File a Service Request with Altera and see if they come up with a better explanation.

Keep in mind that the main objective of Quartus is for optimal design synthesis, not for probing, so I'd argue that eliminating redundant logic, unless I tell it not to via a synthesis attribute, is the correct thing to do.

Cheers,

Dave