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I am using SignalTap to monitor the runtime-signals of my verilog design. However, I just have the situation, that after compiling the whole design in Quartus and when I want to add signals to SignalTap setup for monitoring, that using the SignalTap: pre-synthesis filter for some weird reasons some registers are enlisted, but some are not?!
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The nodes are probably still there, the names are just not present at the level of the hierarchy you want to probe at. You can add synthesis 'keep' and 'preserve' attributes to signals, eg.,
// PLL locked
// (the synthesis attributes allow SignalTap II use)
logic pll_locked_raw /* synthesis keep */;
logic pll_locked_filtered /* synthesis keep */;
Then resynthesize the design, open SignalTap, and add these pre-synthesis nodes (yeah, I know, all presynthesis nodes should really be listed, but they aren't).
Cheers,
Dave
Honored Contributor
