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Altera_Forum
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13 years ago

SginalTap: Some nodes not listed in NodeFinder?!

Hi everyone, I am using SignalTap to monitor the runtime-signals of my verilog design. However, I just have the situation, that after compiling the whole design in Quartus and when I want to ad...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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How can this be?

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Its hard to say. There are several synthesis attributes - you could try a couple of others to see if it makes any difference.

If you're at the top-level of the design, you can always route the signal to an I/O pin. This may force Quartus to eliminate some optimizations - you don't have to probe the I/O pins, you still use SignalTap - its just a way to try and figure out what is going on.

Cheers,

Dave