several warnings using altlvds

Hi all,

i am trying to implement an receiving interface to an ADC (TI ADS6444) using Megafunction ALTLVDS/ALTLVDS_RX.

I have created 2 projects one in Quartus 9.1 SP2 the other in 10.1 SP1. Both share the same problems.

options: 700 Mbps, 7 bit, 4 channels (for the beginning), odd RAM buffer, internal PLL, 90 degrees phase alignment, using bitclk as inclk 350 MHz

In sdc file i just use: "derive_pll_clocks" and "derive_clock_uncertainty".

I am getting several warnings that i cannot interpret.

1)

Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

name: PLL Compensation

ignored entity: rx2_lvds_ddio_in

ignored to: ddio_h_reg*

ignored value: on

ignored source: compiler or hdl assignment

2)

Warning: PLL cross checking found inconsistent PLL clock settings:

Warning: Clock: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[0] with master clock period: 1.000 found on PLL node: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[0] does not match the master clock period requirement: 2.857

Warning: Clock: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[1] with master clock period: 1.000 found on PLL node: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[1] does not match the master clock period requirement: 2.857

Warning: Clock: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[2] with master clock period: 1.000 found on PLL node: rx_inst|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[2] does not match the master clock period requirement: 2.857

3)

Critical Warning: Timing requirements not met

For all three models (slow, fast, 85C) there are negative setup slacks.

Maybe one of you knows something about that warnings. Whether they can be ignored or not. Thanks a lot!