several warnings using altlvds

Thank you josyb,

does your design handle 350 MHz DDR in speed grade 7 Cyclone III?

I already know that some people in this forum disadvice from using ALT_LVDS / ALT_LVDS_RX especially for odd factors.

If i knew the use of constraints better, i would like to try writing my own deserializer.

Now timing is met only for the fast model. What does this mean in respect to the speed grade of the device? Is it right, that a speed grade C6 Cyclone won't be as slow as the "slow model"?

How can one constrain the timing analyze on C6 grades (varying only Temp and Volt), if slow always means C8 (Slowest speed grade in device density) and fast always means best voltage and temp conditions?