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In sdc file i just use: "derive_pll_clocks" and "derive_clock_uncertainty".
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You also need to create your base clock(s), otherwise TimeQuest assumes it is 1.0 GHz! Hence the warnings in your section 2) and obviously you won't be able to make any timing as documented in your section 3).
I don't know how to interpret your warning 1) as this may be a 'design' issue but could also be a valid 'ignored assignment'.
It is a good idea to work to keep the generated warnings to a minimum, I'd say to zero but when using third-party or even Altera IP this is not always possible.
Honored Contributor
