New Contributorset_max_skew timing issue for DDR2 emif on MAX 10
Hello,
I have a timing issue on my design using DDR2 controller on max 10 fpga.
In the generated sdc file for the DDR2 controller I have two skew constraints (cf. below):
##################
# #
# READ DATA PATH #
# #
##################
foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
foreach { dq_pin } $dq_pins {
set_max_skew -from [get_ports $dq_pin] 0.1
}
}
#########################
# #
# FALSE PATH #
# #
#########################
foreach { dqs_pin } $dqs_pins { dq_pins } $q_groups {
foreach { dq_pin } $dq_pins {
set_false_path -from [get_registers *dq_ddio_io*oe_path_enhanced_ddr.fr_oe_data_ddio~DFF*] -to [get_ports $dq_pin]
}
}
set_false_path -rise_from [ get_clocks ${local_pll_write_clk} ] -to [ get_ports $ac_pins ]
foreach { pin } [concat $dqs_pins $dqsn_pins $ck_pins $ckn_pins] {
set_max_skew -to [get_ports $pin] 0.1
}
At the end of fitting I have no timings errors. But, when I launch TimeQuest and generate all summaries report I have max skew timing violations for both constraints.
I'm using quartus prime standard 16.1 (and I have the same problem with 21.1 version)
Can anyone help me please to fix the problem?
Best regards
Hi Amine,
I'm agree with your assumption.
Since this is a soft controller, the timing constraint that has been generated may not fix to the design.
I think you can increase the max skew to meet the timing requirement for each port.
Regards,
Adzim
