Forum Discussion
set_max_skew timing issue for DDR2 emif on MAX 10
- 3 years ago
Hi Amine,
I'm agree with your assumption.
Since this is a soft controller, the timing constraint that has been generated may not fix to the design.
I think you can increase the max skew to meet the timing requirement for each port.
Regards,
Adzim
Hello Sir,
Thank you for submitting your question in Intel Community.
I'm Adzim an application engineer will assist you on this thread.
Are you able to provide more details regarding to the timing violation issue?
Is there any simple design that I can use to replicate the issue?
Regards,
Adzim
- fpgauser3 years ago
New Contributor
Hello Adzim,
Thank you for you reply.
You can find below (enclosed) screenshots of the timings violations that I have.For the first violation (related to the 2nd set_max_skew constraint of the SDC), it seems to be normal because, the DQS is generated with pll1|clk[0]_dq_write_clk while, the path violated use pll1|clk[0]_write_clk as launch clock which is 90° phase shiftted. So, the skew constraint of 100ps is unachievable.
The second violation (related to the 1st set_max_skew constraint of the SDC) seems to be only for fitter (overconstraint) and I guess that I should not consider it at the end of my STA analysis.
Could you please confirm my assumptions?
The controller is a soft IP generated by quartus prime software 16.1 and the sdc as well.
The IO locations were defined according to intel recommendations.Best Regards,
Amine