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fpgauser's avatar
fpgauser
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3 years ago
Solved

set_max_skew timing issue for DDR2 emif on MAX 10

Hello, I have a timing issue on my design using DDR2 controller on max 10 fpga. In the generated sdc file for the DDR2 controller I have two skew constraints (cf. below): ################## ...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi Amine,


    I'm agree with your assumption.

    Since this is a soft controller, the timing constraint that has been generated may not fix to the design.

    I think you can increase the max skew to meet the timing requirement for each port.


    Regards,

    Adzim


fpgauser's avatar
fpgauser
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3 years ago

Hi Adzim,

Thank you for your reply.

Increasing the constraint is not appropriate for our project because, we must do this whenever we regenerate the IP.

So, we decided to keep the violations and add justifications in our design document.

Best regards,

Amine