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fpgauser's avatar
fpgauser
Icon for New Contributor rankNew Contributor
3 years ago
Solved

set_max_skew timing issue for DDR2 emif on MAX 10

Hello, I have a timing issue on my design using DDR2 controller on max 10 fpga. In the generated sdc file for the DDR2 controller I have two skew constraints (cf. below): ################## ...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi Amine,


    I'm agree with your assumption.

    Since this is a soft controller, the timing constraint that has been generated may not fix to the design.

    I think you can increase the max skew to meet the timing requirement for each port.


    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Amine,


Thank you for the update. I'm now transition this thread to community support.

If you have a new question, feel free to open a new thread to get support from Intel expert.

Otherwise, the community users will continue to help you on this thread.


Thank you.

Regards,

Adzim