Forum Discussion

fpgauser's avatar
fpgauser
Icon for New Contributor rankNew Contributor
3 years ago
Solved

set_max_skew timing issue for DDR2 emif on MAX 10

Hello, I have a timing issue on my design using DDR2 controller on max 10 fpga. In the generated sdc file for the DDR2 controller I have two skew constraints (cf. below): ################## ...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi Amine,


    I'm agree with your assumption.

    Since this is a soft controller, the timing constraint that has been generated may not fix to the design.

    I think you can increase the max skew to meet the timing requirement for each port.


    Regards,

    Adzim


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

It's difficult without seeing the project or the timing report errors, but I'd guess the I/O locations you've selected are causing the issue. The Fitter can't meet the requirements to the pins you've selected. This is MAX 10, so I'm guessing this is a soft controller so it could be placed anywhere in the device. Check how the Fitter is placing the controller logic. There may be some other constraints on placement.