set_clock_groups notes

Once you separate clock groups as asynchronous, is there any way to still lightly constrain the paths that cross the clock domains?

Without some loose constraints, FPGA routing can add extraordinary delays, and in extreme cases you could have problems. Two examples might include (1) grey coded fifo pointers, or (2) a synchronized read strobe accompanied by an unsynchronized address.

It is for this reason that I have usually specified multicycle paths for what are really asynchronous crossings, though the asynchronous groups are much less complicated. Sometimes I get odd results with the multicycle paths, too, requiring 3 or even 4 as the cycle count.

\c