Serial Lite IV - Rx Simulation Issues

Hello,

I'm having trouble with the RX in side when simulating the F-Tile Serial Lite IV example design.  

Enviroment:
- Quartus Prime Pro Edition 26.1, Windows
- Questa Altera FPGA Edition-64 2025.3, installed with Quartus 26.1, with its precompiled device libraries
- Device AGMF039R47A1E1VC (Agilex 7 M-Series)
- F-Tile Serial Lite IV IP: FGT, NRZ, 8 lanes, 18.0048 Gbps, RS-FEC enabled, FULL streaming mode,
  PMA reference clock 180.048 MHz, System PLL 562.65 MHz
- Example design generated from the IP parameter editor (Generate Example Design).

Problem 1 :

the generated run_mentor.tcl cannot compile the device libraries. run_mentor.tcl sets QUARTUS_SIM_LIB_DIR to $QUARTUS_ROOTDIR/eda/sim_lib2, DEVICES_SIM_LIB_DIR to $QUARTUS_ROOTDIR/../devices/sim_lib2 and ENABLE_QE_LIBRARY_COMPILATION to true. Both folders exist, but dev_com fails with vlog-7 (Failed to open design unit file) on the first file of every device library : quartus/eda/sim_lib2 : 220model.v, sgate.v, altera_primitives.v, altera_mf.v, altera_lnsim.sv, tennm_atoms.sv, tennm_hssi_atoms.sv, ctfb_hssi_atoms.sv, ctr_hssi_atoms.sv devices/sim_lib2 : tennm_fm_hps.sv, tennm_fp8_noc.sv, tennm_revb_io96.sv, tennm_revb_io96_iopll.sv ,ctfb_hssi_atoms_ncrypt.sv and ctfb_hssi_atoms2_ncrypt.sv, which the script also compiles, are not present anywhere

in the installation. The only ctfb_hssi_atoms file installed is questa_fe/intel/verilog/src/ctfb_hssi_atoms.sv.

Problem 2 : with the precompiled libraries the rx never comes up

To get past problem 1, the two sim_lib2 lines were removed from run_mentor.tcl and ENABLE_QE_LIBRARY_COMPILATION
was set to false, so the design binds to the precompiled Questa Altera FPGA Edition libraries. The macros in
USER_DEFINED_VERILOG_COMPILE_OPTIONS were left as generated. Compilation and elaboration then succeed, and :

- Phy TX Lanes Stable and Phy EHIP ready assert at 58,215 ns, TX link_up at 58,223 ns.
- rx_pcs_fec_phy_reset_n is released at about 200 ns together with the TX, and rx_reset_ack asserts during the
  reset and clears after the release.
- rx_cdr_lock stays 0 on all 8 lanes and rx_link_up never asserts : the testbench stays at "Waiting for RX Link Up".
  The run was stopped at 126.5 us, 68 us after TX link up. The reference logs in UG-20325 show RX link up 20 to
  28 us after TX link up.
- The F-tile model reports a single lane state change per lane, "State change from S0, R0, W0 TO S2, R0, W0",
  finished at 3,625 ns, and nothing after that.
- The simulation runs at about 5 hours of wall-clock time for 126.5 us.

Our own design, which uses the same IP, behaves identically on this installation.

Questions

1. Where should the files that run_mentor.tcl expects in quartus/eda/sim_lib2 and devices/sim_lib2 come from ?
   Is an installation component missing ?
2. Is the example design supported with the precompiled Questa Altera FPGA Edition libraries ? If so, what does
   the FGT RX need to reach rx_cdr_lock ?
3. Is this a known issue in 26.1, and is there a patch or a workaround ?