Running into infinite loop problems

Question

I'm relatively new to Quartus and I'm trying to define a latch with three outputs and the following properties:

L M | Q(t+1) | R(t+1) | S(t+1)

------------------------------

0 0 | S(t) | Q(t) | R(t)

0 1 | 0 | 1 | 1

1 0 | 1 | 0 | 1

1 1 | Q(t) | R(t) | S(t)

So I wrote the following code to do it. Running a functional simulation gets me in an infinite loop. Running a timing simulation results in unanticipated resulting waveform. Perhaps my VHDL code is wrong?

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY newlatch IS

PORT (L,M,Clk : IN STD_LOGIC;

Q,R,S : OUT STD_LOGIC);

END newlatch;

ARCHITECTURE Behavior OF newlatch IS

SIGNAL LM: STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL Q1: STD_LOGIC;

SIGNAL R1: STD_LOGIC;

SIGNAL S1: STD_LOGIC;

BEGIN

PROCESS(L,M)

BEGIN

LM<=L & M;

IF Clk = '1' THEN

IF LM = "00" THEN

Q1<=S1;

R1<=Q1;

S1<=R1;

ELSIF LM = "01" THEN

Q1<='0';

R1<='1';

S1<='1';

ELSIF LM= "10" THEN

Q1<='1';

R1<='0';

S1<='1';

END IF;

Q<=Q1;

R<=R1;

S<=S1;

END IF;

END PROCESS;

END Behavior;

altera_forum · Answer

In FPGA's defining a latch can give you infinite loop in simulation. Latches have combination feedback, in fpga's the timing is hard to define so it is recomended the you do I synchornous design and not I asynchornous design. Due to the nature of FPGA's I would start with a D-flip-flop. You could take a look  Quartus II Handbook :recommended hdl coding styles (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) for more advice.

altera_forum · Answer

I'm pretty sure I'm using synchronous clock. I set it to timing simulation but, my simulation gives the following resulting waveform which doesn't appear to do what the specifications and code tell it to do.

http://img412.imageshack.us/img412/1143/81734182dl8.png

altera_forum · Answer

I haven't synthesized your design, but some quick recommendations:

1) I don't see a clk'EVENT, so you're not synchronous(in the sense that nothing changes at the edge of the clock.)

2) If you do make this edge sensitive, make two processes out of it, one based solely on (clk), and then one that is combinatorial.

3) For some reason you may not want to use the registers. If so, please explain why and what you're trying to do. The registers are the basic building block of the FPGA, and are essentially free. If you try not to use them and want everything as latches, you're asking for trouble. (Maybe not trouble, but minimally an in-efficient use of the silicon provided.) There are cases this is warranted, but please explain.

altera_forum · Answer

I want it to be level sensitive so I don't want it to change at the clock edge.  I only want things to be able to change when clock is high.  I'm trying to design a latch that behaviorally does what I specify it does.  However things aren't working out the way I want them to and I don't quite undersatand why

altera_forum · Answer

I missed this when I first looked at the code, but I'm not sure what is supposed to happen when L=0 and M=0. I thought everything just held their values(like a latch does), but they hold someone else's value, in a roundabout way. Conceptually, a latch is an output that feeds back on itself and into a mux(the select line of the mux is the latch's gate). What you're describing is a cross-connect and I'm not surprised they start toggling.

Ignoring the other states, in this condition you have three nodes where Q <= S <= R <= Q <= S <= R <= etc., i.e. something that will toggle unless S = Q = R.

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Running into infinite loop problems

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