Running into infinite loop problems

I haven't synthesized your design, but some quick recommendations:

1) I don't see a clk'EVENT, so you're not synchronous(in the sense that nothing changes at the edge of the clock.)

2) If you do make this edge sensitive, make two processes out of it, one based solely on (clk), and then one that is combinatorial.

3) For some reason you may not want to use the registers. If so, please explain why and what you're trying to do. The registers are the basic building block of the FPGA, and are essentially free. If you try not to use them and want everything as latches, you're asking for trouble. (Maybe not trouble, but minimally an in-efficient use of the silicon provided.) There are cases this is warranted, but please explain.