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Altera_Forum
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18 years ago

Running into infinite loop problems

I'm relatively new to Quartus and I'm trying to define a latch with three outputs and the following properties: L M | Q(t+1) | R(t+1) | S(t+1) ------------------------------ 0 0 | S(t) ...
Altera_Forum's avatar
Altera_Forum
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18 years ago

In FPGA's defining a latch can give you infinite loop in simulation. Latches have combination feedback, in fpga's the timing is hard to define so it is recomended the you do I synchornous design and not I asynchornous design. Due to the nature of FPGA's I would start with a D-flip-flop. You could take a look Quartus II Handbook :recommended hdl coding styles (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) for more advice.