RTL Viewer

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The statement of "multiple architectures exist but it seems noone want to deal with it" is incorrect, in fact configurations are covered in the first section of the LRM!

Similarly if you have create multiple architectures and they are always all compiled will mean that every architecture must be syntactically correct or the compilation will fail. I think this would cause more (justifiable) criticism than the way it currently works.

At the end of the day the vendors tools are limited by the LRM and the functionality of their competitors' tools, irrespective of who they are.

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Thats not what is being asked.

The OP wants to synthesise all architectures in parrallel so he can chose which one to use during the fit phase.

:) as mentioned above by @kaz "the learners need different version of tools in order to learn best way".

quartus able to compile multiple vhdl architecture <- good

but it can not open in rtlview vhdl architecture your choosed. it chooses for your. <- bad

at fit phase you deal more with chip architecture for lut, alm. here your can return to your code to redesign it.

but you start working with project at Analysis and Elaboration but not at Analysis and Synthesis.

Why does stage Analysis and Elaboration exist ? to check syntax? i don't think so.

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It is a syntax check and hierarchy builder.

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with netlist writer :) and also possibility for simulation.

try to push more variables in you vhdl-code rather than signals and you will see the difference in rtlviewer.

but only if variable is not pure alias for signal.