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Altera_Forum
Honored Contributor
Honored ContributorRTL Viewer
Hi. If I have one file written in VHDL with two different architectures could I see in RTL Viewer structure for each architecture? or the architecture shown in rtlviewer wil be randomly selected b...
Altera_ForumHonored Contributor
Honored Contributor:) as mentioned above by @kaz "the learners need different version of tools in order to learn best way".
quartus able to compile multiple vhdl architecture <- good but it can not open in rtlview vhdl architecture your choosed. it chooses for your. <- bad at fit phase you deal more with chip architecture for lut, alm. here your can return to your code to redesign it. but you start working with project at Analysis and Elaboration but not at Analysis and Synthesis. Why does stage Analysis and Elaboration exist ? to check syntax? i don't think so.
