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Altera_Forum
Honored Contributor
Honored ContributorRTL Viewer
Hi. If I have one file written in VHDL with two different architectures could I see in RTL Viewer structure for each architecture? or the architecture shown in rtlviewer wil be randomly selected b...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- It is a syntax check and hierarchy builder. --- Quote End --- with netlist writer :) and also possibility for simulation. try to push more variables in you vhdl-code rather than signals and you will see the difference in rtlviewer. but only if variable is not pure alias for signal.
