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GLous's avatar
GLous
Icon for New Contributor rankNew Contributor
7 years ago

RTL viewer problem with array of buses, it separates all bits.

I have an VHDL code that uses arrays of buses, I'm reading 10 groups of 4 ASICS of 16 bits each, the problem is that RTL is showing me each bit separately so is showing a gigantic diagram very difficult to follow and useless for documentation.

I'm using Quartus Pro 18.0

6 Replies

  • GLous's avatar
    GLous
    Icon for New Contributor rankNew Contributor

    Hi,

    Merci, for now I have a workaround for documentation but makes me having extra "for generate loops" all over the code.

    I t seems that RTL viewer was not coded to understand arrays of arrays of std_logic_vectors, in the old altera forums there was a questions of 2010 with the same issue.

    Hope to hear from you soon,

    Guillermo

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    I suspect, it seems to be bug.

    Can you provide the project file(.qpf) so that we can replicate the issue?

    Best Regards

    Vikas Jathar

    (This message was posted on behalf of Intel Corporation)

  • GLous's avatar
    GLous
    Icon for New Contributor rankNew Contributor

    Hi Vikas,

    I'm trying to upload the qpf file but the web gets stuck so I copy here two qpf files, the first one is the project I have been doing that it was created with quartus standard edition on a linux and the new project I've created now because I saw that the qpf file was keeping information of the standard version and no the pro.

    STANDARD

    # -------------------------------------------------------------------------- #
    #
    # Copyright (C) 2018  Intel Corporation. All rights reserved.
    # Your use of Intel Corporation's design tools, logic functions 
    # and other software and tools, and its AMPP partner logic 
    # functions, and any output files from any of the foregoing 
    # (including device programming or simulation files), and any 
    # associated documentation or information are expressly subject 
    # to the terms and conditions of the Intel Program License 
    # Subscription Agreement, the Intel Quartus Prime License Agreement,
    # the Intel FPGA IP License Agreement, or other applicable license
    # agreement, including, without limitation, that your use is for
    # the sole purpose of programming logic devices manufactured by
    # Intel and sold by Intel or its authorized distributors.  Please
    # refer to the applicable agreement for further details.
    #
    # -------------------------------------------------------------------------- #
    #
    # Quartus Prime
    # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
    # Date created = 10:00:10  Juni 10, 2018
    #
    # -------------------------------------------------------------------------- #
     
    QUARTUS_VERSION = "18.0"
    DATE = "10:00:10  Juni 10, 2018"
     
    # Revisions
     
    PROJECT_REVISION = "compactorV01"

    PRO

    # -------------------------------------------------------------------------- #
    #
    # Copyright (C) 2018  Intel Corporation. All rights reserved.
    # Your use of Intel Corporation's design tools, logic functions 
    # and other software and tools, and its AMPP partner logic 
    # functions, and any output files from any of the foregoing 
    # (including device programming or simulation files), and any 
    # associated documentation or information are expressly subject 
    # to the terms and conditions of the Intel Program License 
    # Subscription Agreement, the Intel Quartus Prime License Agreement,
    # the Intel FPGA IP License Agreement, or other applicable license
    # agreement, including, without limitation, that your use is for
    # the sole purpose of programming logic devices manufactured by
    # Intel and sold by Intel or its authorized distributors.  Please
    # refer to the applicable agreement for further details.
    #
    # -------------------------------------------------------------------------- #
    #
    # Quartus Prime
    # Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
    # Date created = 09:15:03  August 15, 2018
    #
    # -------------------------------------------------------------------------- #
     
    QUARTUS_VERSION = "18.0"
    DATE = "09:15:03  August 15, 2018"
     
    # Revisions
     
    PROJECT_REVISION = "UTDataProc"

    In both cases I see the same problem

    Thanks,

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    Thanks & I appreciate your efforts but we need project file to replicate.

    Can you attach that project file(.qpf) as a zip?

    Best Regards

    Vikas Jathar

    (This message was posted on behalf of Intel Corporation)

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    I could able to replicate the issue & presently it is unavailable.

    Once I get any inputs definitely I will reach to you.

    Best Regards

    Vikas Jathar

    (This message was posted on behalf of Intel Corporation)