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GLous's avatar
GLous
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7 years ago

RTL viewer problem with array of buses, it separates all bits.

I have an VHDL code that uses arrays of buses, I'm reading 10 groups of 4 ASICS of 16 bits each, the problem is that RTL is showing me each bit separately so is showing a gigantic diagram very diffic...
GLous's avatar
GLous
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7 years ago

Hi,

Merci, for now I have a workaround for documentation but makes me having extra "for generate loops" all over the code.

I t seems that RTL viewer was not coded to understand arrays of arrays of std_logic_vectors, in the old altera forums there was a questions of 2010 with the same issue.

Hope to hear from you soon,

Guillermo