Occasional ContributorRouting constraints in QPP
I'm aware of Logic Lock feature in QPP, through which I can restrict the placement of a design node on the FPGA chip. How do I restrict the routing of a data path as well as a clock path in QPP? like placing two earlier distant modules near using logic lock may reduce the data path delay but may increase the clock path delay at either the source or destination node.
I'd like to restrict the such path length or at least direct the tool to go for best minimum possible.
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
