Forum Discussion
Pack_of_lone_wolves
Occasional Contributor
Occasional ContributorRouting constraints in QPP
I'm aware of Logic Lock feature in QPP, through which I can restrict the placement of a design node on the FPGA chip. How do I restrict the routing of a data path as well as a clock path in QPP? like...
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
Pack_of_lone_wolvesOccasional Contributor
Occasional ContributorWhat I also suspect and have a question is that what role can pin planning in assignment editor can play in making timing closure more difficult? The project has multiple clocks and I feel that position of the clock pins is responsible for introducing large clock skews.
