Forum Discussion
Occasional ContributorRouting constraints in QPP
This is all handled by clock and other timing constraints. I'd suggest getting familiar with your .sdc file.
User guide: https://www.intel.com/content/www/us/en/docs/programmable/683243.html
Training: https://learning.intel.com/developer/learn/courses/201/understanding-timing-analysis-in-fpgas, https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software
Super ContributorThat is correct, synchronization of the reset is usually a common practice that we do in FPGA. Especially we want to check the recovery and removal time.
Unless you send us your design, it will be hard for me to analyze on this., For your situation, leverate the DRC to look for high tension register, and start duplicating it. I will send you more steps that can be automate after you pipeline the register.
