ROPUF Implementation on Max10 FPGA - Chip Planner help

Question

Hey there!I am a college student working on implementing a ring-oscillator-based PUF on the Max10 FPGA (specifically the 10M50DAF484C7G). I have synthesized the design and programmed it to my board, but I am afraid that there are delays in my design that I have not accounted for due to the random placement of the logic cells. If possible, I would like to arrange these cells and the blocks within so that there is a consistent distance between the end of each ring oscillator and the input to the multiplexor. Is there a way to use the chip planner tool to place the specific element I want in a certain location in a specific cell? Can I use TCL scripting to do this? Thanks for any help, I will include some pictures below The picture of the chip planner shows two large clusters. The leftmost is all ring oscillator signals, while the other cells are muxes, counters, comparators, etc.The picture of the RTL view shows most of the components and the connections between them. Some ring oscillators are cut off from the image so that the other components are readable.

sstrell · Answer

What do your timing constraints (.sdc) look like? Is your design meeting timing? You could use set_max_skew to help match routing lengths, but check to see if your base timing constraints are meeting timing first.

What's your goal with the matched lengths?

asperkins · Answer

## Generated SDC file "ROPUF.sdc"

## Copyright (C) 2018  Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Intel Program License 
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors.  Please
## refer to the applicable agreement for further details.

## VENDOR  "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"

## DATE    "Wed Jun 26 17:48:37 2024"

##
## DEVICE  "10M50DAF484C7G"
##

#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {choice[0]} -period 100.000 -waveform { 0.000 50.000 } [get_ports {choice[0]}]

#**************************************************************
# Create Generated Clock
#**************************************************************

#**************************************************************
# Set Clock Latency
#**************************************************************

#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {choice[0]}] -rise_to [get_clocks {choice[0]}]  0.020  
set_clock_uncertainty -rise_from [get_clocks {choice[0]}] -fall_to [get_clocks {choice[0]}]  0.020  
set_clock_uncertainty -fall_from [get_clocks {choice[0]}] -rise_to [get_clocks {choice[0]}]  0.020  
set_clock_uncertainty -fall_from [get_clocks {choice[0]}] -fall_to [get_clocks {choice[0]}]  0.020

#**************************************************************
# Set Input Delay
#**************************************************************

#**************************************************************
# Set Output Delay
#**************************************************************

#**************************************************************
# Set Clock Groups
#**************************************************************

#**************************************************************
# Set False Path
#**************************************************************

#**************************************************************
# Set Multicycle Path
#**************************************************************

#**************************************************************
# Set Maximum Delay
#**************************************************************

#**************************************************************
# Set Minimum Delay
#**************************************************************

#**************************************************************
# Set Input Transition
#**************************************************************I have attached the contents of my .sdc file, and all of my reports are meeting timing. My goal with the matched lengths is to get rid of unwanted delays in the physical connections between the output of each ring oscillator and the input of the multiplexor. I would like for there to be a "standardized" length so that one oscillator is not significantly slower than another due to the propagation delay of the signal through the wire.

sstrell · Answer

You have no set_input_delay or set_output_delay constraints so your design is not fully constrained for timing. As such, the Fitter has no guide for how to place the internals of your design. Add set_input_delay and set_output_delay constraints for your I/O first before trying to make adjustments like this to the internals. If you don't know the timing specs/requirements of the "upstream" and "downstream" devices, you could use set_max_delay and set_min_delay to constrain the I/O paths with specific delay values.

After you've constrained the I/O, if you still need to match delays internally, you can, but fully constraining the design must be done first.

shengn_altera · Answer

Is there a way to use the chip planner tool to place the specific element I want in a certain location in a specific cell? Can I use TCL scripting to do this?For this, you can use set location assignment check this link https://www.intel.com/content/www/us/en/docs/programmable/683641/24-1/location-assignment-optimization-guidelines.htmlCan set in assignment editor as well.

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ROPUF Implementation on Max10 FPGA - Chip Planner help

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