ROPUF Implementation on Max10 FPGA - Chip Planner help

You have no set_input_delay or set_output_delay constraints so your design is not fully constrained for timing. As such, the Fitter has no guide for how to place the internals of your design. Add set_input_delay and set_output_delay constraints for your I/O first before trying to make adjustments like this to the internals. If you don't know the timing specs/requirements of the "upstream" and "downstream" devices, you could use set_max_delay and set_min_delay to constrain the I/O paths with specific delay values.

After you've constrained the I/O, if you still need to match delays internally, you can, but fully constraining the design must be done first.