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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

rom and ram

I'm stucked i dont know what to do

1 Testprotokol (verifiering och validering)

2 Deskribe with pulsediagrams (from ModelSim) and write and read cykel for RAM.

3 Deskribe med pulsediagram (from ModelSim) one read cykel for ROM

Test bench

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY uppgift_3b_vhd_tst IS

END uppgift_3b_vhd_tst;

ARCHITECTURE uppgift_3b_arch OF uppgift_3b_vhd_tst IS

-- constants

-- signals

SIGNAL addr_ram : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL addr_rom : STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL clk : STD_LOGIC:='0';

SIGNAL data_ram : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL q_ram : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL q_rom : STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL we_ram : STD_LOGIC;

COMPONENT uppgift_3b

PORT (

addr_ram : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

addr_rom : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

clk : IN STD_LOGIC;

data_ram : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

q_ram : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

q_rom : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

we_ram : IN STD_LOGIC

);

END COMPONENT;

BEGIN

i1 : uppgift_3b

PORT MAP (

-- list connections between master ports and signals

addr_ram => addr_ram,

addr_rom => addr_rom,

clk => clk,

data_ram => data_ram,

q_ram => q_ram,

q_rom => q_rom,

we_ram => we_ram

);

clk<= not(clk) after 20 ns;

init : PROCESS

-- variable declarations

BEGIN

-- test protokoll case 1

WAIT FOR 100ns;

addr_ram <= "001";

-- test protokoll case 2

WAIT FOR 100ns;

addr_rom <= "10";

-- test protokoll case 3

WAIT FOR 100ns;

data_ram <= "011";

-- test protokoll case 4

WAIT FOR 100ns;

we_ram <= '1';

-- code that executes only once

WAIT;

END PROCESS init;

END uppgift_3b_arch;

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I'm not entirely sure what the exact problem you are asking about (as I assume english isn't your primary language)

    Try replacing: 

    clk<= not(clk) after 20 ns;

    With: 

        
PROCESS
BEGIN
    wait for 20 nS;
    clk <= not clk;
END PROCESS;

    For anyone else who may want to see the unmodified code with proper indents: 

    LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
ENTITY uppgift_3b_vhd_tst IS
END uppgift_3b_vhd_tst;
ARCHITECTURE uppgift_3b_arch OF uppgift_3b_vhd_tst IS
-- constants 
-- signals 
SIGNAL addr_ram : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_rom : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL clk      : STD_LOGIC:='0';
SIGNAL data_ram : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL q_ram    : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL q_rom    : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL we_ram   : STD_LOGIC;
COMPONENT uppgift_3b
    PORT 
    (
        addr_ram    : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
        addr_rom    : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        clk         : IN STD_LOGIC;
        data_ram    : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
        q_ram       : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
        q_rom       : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
        we_ram      : IN STD_LOGIC
    );
END COMPONENT;
BEGIN
i1 : uppgift_3b
    PORT MAP 
    (
        -- list connections between master ports and signals
        addr_ram => addr_ram,
        addr_rom => addr_rom,
        clk      => clk,
        data_ram => data_ram,
        q_ram    => q_ram,
        q_rom    => q_rom,
        we_ram   => we_ram
    );
    
clk<= not(clk) after 20 ns;
init : PROCESS 
-- variable declarations 
BEGIN
    -- test protokoll case 1
    WAIT FOR 100ns;
    addr_ram <= "001";
    -- test protokoll case 2 
    WAIT FOR 100ns;
    addr_rom <= "10";
    -- test protokoll case 3
    WAIT FOR 100ns;
    data_ram <= "011";
    -- test protokoll case 4
    WAIT FOR 100ns;
    we_ram <= '1';
    -- code that executes only once 
    WAIT; 
END PROCESS init; 
END uppgift_3b_arch;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Try replacing: 

    clk<= not(clk) after 20 ns;
    With: 

        
PROCESS
BEGIN
    wait for 20 nS;
    clk <= not clk;
END PROCESS;

    --- Quote End ---

    Why did you suggest this change? the origional code is perfectly valid and will work exactle the same as the process. Is it just a question of coding style?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you very much for your help.I'm from sweden and i don't speak english very often.... with kind regards Per :)

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Why did you suggest this change? the origional code is perfectly valid and will work exactle the same as the process. Is it just a question of coding style?

    --- Quote End ---

    I was not 100% sure if it would result in the same behavior. I guess I'm just used to seeing people using transport delays outside of processes and testbench clocks inside processes.