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Altera_Forum's avatar
Altera_Forum
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13 years ago

rom and ram

I'm stucked i dont know what to do 1 Testprotokol (verifiering och validering) 2 Deskribe with pulsediagrams (from ModelSim) and write and read cykel for RAM. 3 Deskribe med pulsediag...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Why did you suggest this change? the origional code is perfectly valid and will work exactle the same as the process. Is it just a question of coding style?

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I was not 100% sure if it would result in the same behavior. I guess I'm just used to seeing people using transport delays outside of processes and testbench clocks inside processes.