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fflores's avatar
fflores
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1 year ago

RiscFree Arria10 Ashling Sample project does not build

Hello,

I am trying to use one of the Ashling Sample project (Arria10-A9-Sum) from the RiscFree IDE for Intel that comes with the "Intel Quartus Prime Standard Edition" windows installation, but the project does not build and it seems like is missing a plugin since the property setting shows a 'Orphaned configuration' warning as shown in the attachments. Does anyone know how to resolve this issue? any help will be greatly appreciated.

4 Replies

    • fflores's avatar
      fflores
      Icon for New Contributor rankNew Contributor

      Hello Jingyang, Teh,

      I am importing a sample project for the ARM HPS. The HPS link does not have any issues for the Agilex A53 sample which comes with a pre-built 'elf' file. However, if I apply the same steps for the Arria10 sample then the project does not compile as shown in the original post attachment(Arria10-a9-sum- Does not build.PNG) and if I go into the Arria10 Sample project 'Properties->c/c++ build->settings->Tool Settings', then it shows as blank(Arria10-a9-sum- Orphaned configuration.PNG) with an "Orphaned Configuration...." warning. and Since the project does not build then it cannot create a debug session. I was wondering if there are other steps for the Arria10 to work on RiscFree IDE. As a additional test, I did the same steps with Cyclone V sample project, which gets the same type of error.

      The RiscFree IDE version that come with the "Intel Quartus Prime Standard Edition" is v23.4.1

      Regards,

      Fernando

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi Fernando


    Sorry for the late response.

    Regret to inform you that currently the Ashling IDE only supports debugging feature for the SOC.

    For building a sample project you would need to stick back to using the Arm Development IDE.


    Building sample project in ArmDS.

    https://www.rocketboards.org/foswiki/Documentation/SoCEDS#Exercise_Sample_Application


    Debugging on Ashling IDE

    https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/Debugging-SoC-FPGA-with-RiscFree-IDE/m-p/1597064#M2561


    Regards

    Jingyang, Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi


    Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

    If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


    Regards

    Jingyang, Teh