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Honored ContributorRISC 16 sequential implementation in vhdl
I am working now on implementing a 16 bit RISC CPU in VHDL, the instruction set consists of 8 instructions 16 bits each.
the architecture of the data path and instruction flow is attached , i need your help how to start implementation? could you give me examples for source codes like this architectur2 Replies
Altera_ForumHi,
actually I do not understand what you really want to do and how you want us to help you. What I understand is that you want to code your own CPU in VHDL. I can point you to a general idea of a processor, which is part of the Altera University Program Labs. You find the instruction of that Lab here: https://www.altera.com/support/training/university/materials-lab-exercises.html#digital-logic-exercises The labs are called: Lab 9 - A Simple Processor and Lab 10 - An Enhanced Processor. I hope that helps, but again I am not sure what you are doing.- Altera_Forum
This is looks quite interesting, however it will be good if you try to explain more for what you plan to do. are you doing something liek this?
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=8&cad=rja&uact=8&ved=0ahukewix2rgfpvtjahvici4khwp1cwyqfghjmac&url=http%3a%2f%2fwww.eng.auburn.edu%2f~agrawvd%2fcourse%2fe6200_spr12%2fproject%2f5200_6200project_spring2012.pptx&usg=afqjcne3mlgbupsqjtcpjrs1qe5nslge8a&bvm=bv.110151844,d.c2e
