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Honored Contributor
Honored ContributorRISC 16 sequential implementation in vhdl
I am working now on implementing a 16 bit RISC CPU in VHDL, the instruction set consists of 8 instructions 16 bits each. the architecture of the data path and instruction flow is attached , i need...
Altera_ForumHonored Contributor
Honored ContributorThis is looks quite interesting, however it will be good if you try to explain more for what you plan to do. are you doing something liek this?
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=8&cad=rja&uact=8&ved=0ahukewix2rgfpvtjahvici4khwp1cwyqfghjmac&url=http%3a%2f%2fwww.eng.auburn.edu%2f~agrawvd%2fcourse%2fe6200_spr12%2fproject%2f5200_6200project_spring2012.pptx&usg=afqjcne3mlgbupsqjtcpjrs1qe5nslge8a&bvm=bv.110151844,d.c2e
