Recovery timing errors using clock crossing bridge

Question

I am using a Cyc III/Nios II with the DDR SDRAM HP controller in half rate mode. The controller in half rate mode (to support my SDRAM CAS latency of 2 or 2.5) creates three clocks - the sysclk, auxfull, and auxhalf. Ultimately my CPU is clocked at 100MHz, and the DDR controller is 75MHz (auxhalf) and the DDR memory frequency (auxfull) is 150MHz. So I have a clock crossing bridge in between the cpu and the ddr sdram hp controller. My settings and interconnection is very similar to the Cyclone III EP3C25 dev kit design. Even with the dev kit design from Altera - with maximum effort, the design fails lots of recovery/removal paths related to the clock crossing bridge dcfifo.

No matter how much effort I put into synthesis and the fit - I get many recovery timing errors related to the clock crossing bridge's "DCFIFO". Specifically, the 'FROM' for the failing path always contains the word 'reset' indicating that it's a reset recovery. FYI - the design works and functions 100% properly on the target.

An example failing path is:

from:

Mysystem_SOPC_reset_com_cpu_clk_domain_synch_module:Mysystem_SOPC_reset_com_cpu_clk_domain_synch|data_out

to:

Mysystem_SOPC_reset_com_cpu_clk_domain_synch_module:Mysystem_SOPC_reset_com_cpu_clk_domain_synch|data_out -> Mysystem_SOPC:Mysystem_SOPC_inst0|com_cpu_ddr_clock_crossing_bridge:the_com_cpu_ddr_clock_crossing_bridge|com_cpu_ddr_clock_crossing_bridge_downstream_fifo:the_downstream_fifo|dcfifo:downstream_fifo|dcfifo_5tf1:auto_generated|altsyncram_ri31:fifo_ram|q_b[3]

Any ideas?

altera_forum · Answer

What's the source and destination clock?  Are they related?  I assume not, and you need to cut timing between them in your design.

altera_forum · Answer

thanks for the response and you are correct - they are not related and that's why I'm using a clock crossing bridge...becuase they are not related. The FROM clock is from within the ALT MEM PHY (notice the text alt_m em_phy_clk_reset:clk in there) and the TO clock is the cpu core clock at 100MHz.

from clock:

Mysystem_SOPC:Mysystem_SOPC_inst0|com_cpu_ddr_sdram_0:the_com_cpu_ddr_sdram_0|com_cpu_ddr_sdram_0_controller_phy:com_cpu_ddr_sdram_0_controller_phy_inst|com_cpu_ddr_sdram_0_phy:alt_mem_phy_inst|com_cpu_ddr_sdram_0_phy_alt_mem_phy:com_cpu_ddr_sdram_0_phy_alt_mem_phy_inst|com_cpu_ddr_sdram_0_phy_alt_mem_phy_clk_reset:clk|com_cpu_ddr_sdram_0_phy_alt_mem_phy_pllll|altpll:altpll_component|altpll_62s2:auto_generated|clk[0]

to clock:

I would like to know how to close timing on the Cyclone III dev kit design???? Maybe it's Terasic that designed the SOPC system that ships with the kit - either way as a basis I should be able to get rid of all recovery/removal timing errors in that design, and it would be a good representative design. I'm wondering if it's at all possible to get rid of these errors seeing as how the FROM and TO are all within Altera's IP...

thanks!

altera_forum · Answer

Add the following to your .sdc:

set_clock_groups -asynchronous -group {clkA} -group {clkB}

where the clkA and clkB are the clocks copied right out of the timing summary. Here are some notes on that constraint:

http://www.alteraforum.com/forum/showthread.php?t=18790&highlight=set_clock_groups

SOPC Builder won't do this for you. It often doesn't know the names of the clocks(they may be coming from something outside of SOPC builder), and it can't always be certain that you want timing cut between them. For example, you may treat this interface as asynchronous, but somewhere else you might have data passed between them that is treated synchronously(of course the clocks would have to be synchronous for this to work).

altera_forum · Answer

Thanks for the response and the link, it was helpful. Let me ask a couple questions and make a couple points. So - the intention of this constraint is to tell the timing analyzer (or fitter?) that the various signals, or groups of signals, are asynchronous? Does it actually change something in timing or does it basically get rid of the error by ignoring the paths? I would think that the tools would know that two paths connected on opposite sides of a "clock-crossing bridge" are not synchronous. Otherwise a pipeline bridge could be used instead if everything is synchronous and only registering or buffering is required. As an example design shouldn't the dev kit whose top level design is copyrighted by Altera, and uses Time Quest, be shipped with the design having no failing paths???:confused:

Anyway - I can add what you suggest to the dev kit design's sdc file since it is using TQ. My design is still using the classic timing analyzer becuase I haven't had time to migrate on my current project's budget. Is there a way to accomplish the same thing in the classic timing analyzer?

altera_forum · Answer

In the Assignment Editor, do a Cut Timing assignment from one clock to the other, and then vice-versa.

Actually, I don't mind the clocking being left to the user. It's not to difficult and in reality something I think users need to understand. The one that drives me crazy is development kits without any I/O timing constraints, which users could then use as a template for their own boards, since I/O timing is considerably more complicated.

And yes, it's ignoring the paths(which may change the timing on the next fit, since the fitter can now ignore them too).

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Recovery timing errors using clock crossing bridge

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