Recovery timing errors using clock crossing bridge

Thanks for the response and the link, it was helpful. Let me ask a couple questions and make a couple points. So - the intention of this constraint is to tell the timing analyzer (or fitter?) that the various signals, or groups of signals, are asynchronous? Does it actually change something in timing or does it basically get rid of the error by ignoring the paths? I would think that the tools would know that two paths connected on opposite sides of a "clock-crossing bridge" are not synchronous. Otherwise a pipeline bridge could be used instead if everything is synchronous and only registering or buffering is required. As an example design shouldn't the dev kit whose top level design is copyrighted by Altera, and uses Time Quest, be shipped with the design having no failing paths???:confused:

Anyway - I can add what you suggest to the dev kit design's sdc file since it is using TQ. My design is still using the classic timing analyzer becuase I haven't had time to migrate on my current project's budget. Is there a way to accomplish the same thing in the classic timing analyzer?