Recovery timing errors using clock crossing bridge

thanks for the response and you are correct - they are not related and that's why I'm using a clock crossing bridge...becuase they are not related. The FROM clock is from within the ALT MEM PHY (notice the text alt_m em_phy_clk_reset:clk in there) and the TO clock is the cpu core clock at 100MHz.

from clock:

Mysystem_SOPC:Mysystem_SOPC_inst0|com_cpu_ddr_sdram_0:the_com_cpu_ddr_sdram_0|com_cpu_ddr_sdram_0_controller_phy:com_cpu_ddr_sdram_0_controller_phy_inst|com_cpu_ddr_sdram_0_phy:alt_mem_phy_inst|com_cpu_ddr_sdram_0_phy_alt_mem_phy:com_cpu_ddr_sdram_0_phy_alt_mem_phy_inst|com_cpu_ddr_sdram_0_phy_alt_mem_phy_clk_reset:clk|com_cpu_ddr_sdram_0_phy_alt_mem_phy_pllll|altpll:altpll_component|altpll_62s2:auto_generated|clk[0]

to clock:

Mysystem_SOPC:Mysystem_SOPC_inst0|pll_0:the_pll_0|altpllpll_0:the_pll|altpll:altpll_component|altpll_jgl1:auto_generated|clk[1]

I would like to know how to close timing on the Cyclone III dev kit design???? Maybe it's Terasic that designed the SOPC system that ships with the kit - either way as a basis I should be able to get rid of all recovery/removal timing errors in that design, and it would be a good representative design. I'm wondering if it's at all possible to get rid of these errors seeing as how the FROM and TO are all within Altera's IP...

thanks!