Occasional Contributor
Occasional ContributorHim sstrell, Right ok ...thanks for the update. I must read that UG more then ! It is a pain having to recompile the entire FPGA just to go from an AND to an OR for the trigger though. You don't need to do any of that with Chip Scope Pro for example which to me makes for a much better way to implement a hassle free ILA !!
Best regards
Dr Barry H
Super ContributorHow often do you need to switch a trigger condition column type between Boolean AND and OR? I can't say I've ever needed to do that more than once.
Easy workaround though: add an additional trigger condition column. Set one column to Boolean AND and the other to Boolean OR. You have to do one more compile to set it up, but then, whichever one you want to use (or not use), enable or disable the checkbox at the top of the column. Enabling/disabling a trigger condition column is a runtime change that does not require recompilation or reprogramming of the device. Disabling a column skips over that column. And as mentioned previously, changing value cells within a column is also a valid runtime change that doesn't require recompilation.
Another tip: if you want to avoid accidentally making a change that requires recompilation, set the locking option at the top of the Node list (I forget what it's called but there's a pop-up list there). This grays out any settings that would require a recompile.
Super ContributorAny warnings or errors when you synthesize the design? No way to tell if there's an issue from this snippet.
Super ContributorSettings on the right, set the number of trigger conditions.
Occasional ContributorHi sstrell, Thanks a lot ! I know what you mean ...how often do you switch between AND and OR triggers or even Compares. For me it can be occasionally i suppose in reality. But unless you nail down all your trigger situations BEFORE compiling you never really know do you !
And i guess i got used to the ChipScope Pro way which requires no compiles when you change any of your trigger conditions on existing probes.
But thanks for the explain and yes i see how i can add in columns now to allow more flexible triggers. That is a really helpful suggestion, thanks very much for your detailed replay.
I will also take a look at the LOCK feature you mentioned, that might be of use as well.
One other thing i am having trouble with is State Machines and FSM triggers for an FSM i have written in System Verilog. When i try to add the state register i can't seem to add it at all. It shows up in RED, even though i have it assigned like this in my RTL
My FSM definition is like so:
Occasional ContributorHi sstrell,
Thanks, and No none That i can see. I will verify that though again in the fitter report and post synthesis! I think i see how to do it now...using the 'add state machine nodes...' menu item.
One other point: How do i add in a new trigger column ? I can't see hw to do that in Quartus Standard Edition version 25.1 If i right click for example on the existing trigger column, marked as 1, nothing in the popup menu here offers any way to add in anew Trigger Column. And none of the other menus do either as far as i can see./
Cheers, Dr Barry H
Occasional ContributorThanks sstrell, yes i see that now. And you can have advanced mode as well for triggers. That might be worth investigating. And adding in a Mnemonic text file to link to any State Machines will be useful too :)
cheers, Dr Barry H
