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Scarlet
New Contributor
New ContributorStrange issues on FPGA
Hi All, I wrote a simple finite state machine Verilog code and ran it on the FPGA, but it never runs stably. My environment: - MAX10 10m08 EVB - Quartus Prime Lite 23.1.1 My Verilog Code: ...
ScarletNew Contributor
New ContributorI have a question: why can the FSM jump to an illegal state if the input changes simultaneously with the clock edge?
FvMSuper Contributor
Good question. Main reason is clock and data path delay skew for multiple state variable registers so that one registers "sees" old and other new input state. A state transition from "1000" to "0100" can result in either "0000" or "1100" illegal state. Depending on the implemented logic, the state machine can only recover by a reset. Above mentioned safe state machine logic enforces a transition from illegal to legal, usually initial state.
