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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

quartus pro 25.3 bug?

Now I am developing  a project  with agilex7  base on the quartus pro 25.3.   the project contains R-TILE pcie hard ip and F-tile ethernet hard ip.   During board bring-up debugging, we frequently e...
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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

accorind to r-tile avalon streaming IP  user guide,  the slow_clk is sync to coreclkout_hip.  But during test on-board,  we find that  the slow_clk and coreclkout_hip may lost sync sometimes. so how to debug further? 

RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 month ago

I checked the PIO design and these two clocks you mentioned are from different sources, unlike what I've experienced in other designs. 

You can use a known user clock, normally 50MHz or 100MHz, to sample these two clocks, and monitor them with Transitional Type in a stp to record the changes. To check if they really lose sync, when the situation happens, and how frequent it happens.

Also pls make sure the OSC clock is set in your project. 

 

Regards,

Rong