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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
18 days ago

fanout issue

now I develop a project with agilext7 FPGA,  the sysclk is 416MHz.  the project has still WNS=-500ps TNS=-5000ns violation. from the fitter duplication summary report below, we can see that the mos...
Compilation
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
17 days ago

Can you show the actual failing paths in the timing report (a detailed slack/path report to see all the delay elements along the path)?  Have you looked at the failing paths in the Chip Planner to see if there might be physical factors involved with the placement of the failing paths?

  • zjj's avatar
    zjj
    Icon for Occasional Contributor rankOccasional Contributor
    16 days ago

    the fit summary report is

    there is 48809 failing end points, I give the one path: