Honored ContributorHi,everyone.
I want to use ram in my design. I find some types in Quartus. I don't know what's the detailed differences among them and how to use them, such as how to initialize them.For example, "lpm_ram_dq" , I create it and leave it blank, now i want to use it , how to write " _.mif " to it , can it ? or I have to initialize it when i create it?:confused: Thanks everyone!
Honored Contributorhi,
i asume you want to use the on chip memory. first, the lpm rom/ram functions are not to be used any more. you choud use the altsyncram object. The mif files are louded in to the ram cels(m4k, m9k,...) at configuration time, they are compiled in to the sof or the pof file. these files can be etided via the quartus interface. Reading and writing is very easy, the data is stored or writen to (depends on wren ) wen the block get its clock signal. Here is a link where you can find al the info needed http://www.altera.com/literature/hb/cyc/cyc_c51007.pdf hope this helps you out.Honored ContributorThanks mirimon.
I have found the stuff i need in the pdf. Why does "the lpm rom/ram functions are not to be used any more" ? Any disadvantage or inconvenience?Honored ContributorI'm using the mif to initialize the mem in the pof for our firmware,
this is working great on stratix 2 fpga !Honored ContributorHonored ContributorI think, embedded RAM functionality is similar to Xilinx but not identical. Comparing the RAMB4_S16_S16 primitive with altsyncram Megafunction with appropriate parameters, I see two differences:
1. RST(A/B) is a synchronous clear while altsyncram has an asynchronous clear option. 2. RAMB4_S16_S16 has initialization in generics while altsyncram uses *.mif or *.hex file There may be additional functional differences, but the altsyncram port signals can be parametrized to equal RAMB4_S16_S16 as far as I understand. If your application doesn't depend on synchronous clear for the output registers or initialization in generics, you can write a wrapper that emulates RAMB4_S16_S16 through altysncram.Honored ContributorYou can define a RAM module in Megawizard with properties equal to RAMB4_S16_S16.
You would get a component definition like thiscomponent altRAMB4_S16_S16
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;RAMB4_S16_S16_inst : altRAMB4_S16_S16 PORT MAP (
address_a=> ADDRA, -- Port A 8-bit address input
address_b=> ADDRB, -- Port B 8-bit address input
clock_a => CLKA, -- Port A clock input
clock_b => CLKB, -- Port B clock input
data_a => DIA, -- Port A 16-bit data input
data_b => DIB, -- Port B 16-bit data input
enable_a => ENA, -- Port A RAM enable input
enable_b => ENB, -- Port B RAM enable input
wren_a => WEA, -- Port A RAM write enable input
wren_b => WEB, -- Port B RAM write enable input
q_a => DOA, -- Port A 16-bit data output
q_b => DOB -- Port B 16-bit data output
);You can instantiate the example altRAMB4_S16_S16 also in Verilog. I skipped the step of creating a wrapper module and instantiated the Megawizard generated module directly instead of original RAMB4_S16_S16. You could omit some unused signals, as the port specific clock and the enables, that I used to be compatible with RAMB4_S16_S16 definition.
altRAMB4_S16_S16 mem (
.address_a (ADDRA),
.address_b (ADDRB),
.clock_a (clk),
.clock_b (clk),
.data_a (DINA),
.data_b (DINB),
.enable_a (1'b1),
.enable_b (1'b1),
.wren_a ( WE),
.wren_b ( WE),
.q_a (DOUTA),
.q_b (DOUTB)
);I included a Wraper instead of editing your file and the design could be compiled. 9 RAM blocks had been used. Of course I couldn't easily check the design for correct function.
Honored ContributorThe error is due to the fact, that you didn't include the previously posted altRAMB4_S16_S16.v to your design directory, which contains the Megwizard generated RAM. The wrapper references this design file, as you easily can see from the text.
