rams in Quartus

You can define a RAM module in Megawizard with properties equal to RAMB4_S16_S16.

You would get a component definition like this

component altRAMB4_S16_S16
PORT
(
  address_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  address_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  clock_a	: IN STD_LOGIC ;
  clock_b	: IN STD_LOGIC ;
  data_a	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
  data_b	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
  enable_a	: IN STD_LOGIC  := '1';
  enable_b	: IN STD_LOGIC  := '1';
  wren_a	: IN STD_LOGIC  := '1';
  wren_b	: IN STD_LOGIC  := '1';
  q_a		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
  q_b		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;

In the wrapper architecture, you instantiate this module using the RAMB4_S16_S16 port names:

RAMB4_S16_S16_inst : altRAMB4_S16_S16 PORT MAP (
  address_a=> ADDRA, -- Port A 8-bit address input
  address_b=> ADDRB, -- Port B 8-bit address input
  clock_a	 => CLKA, -- Port A clock input
  clock_b	 => CLKB, -- Port B clock input
  data_a	 => DIA, -- Port A 16-bit data input
  data_b	 => DIB, -- Port B 16-bit data input
  enable_a	 => ENA, -- Port A RAM enable input
  enable_b	 => ENB, -- Port B RAM enable input
  wren_a	 => WEA, -- Port A RAM write enable input
  wren_b	 => WEB, -- Port B RAM write enable input
  q_a	 => DOA, -- Port A 16-bit data output
  q_b	 => DOB  -- Port B 16-bit data output
);

In the wrapper entity, you export the RAMB4_S16_S16 port names. You could shorten this action by simply renaming the ports in the wizard generated designfile, but then it could be no longer edited by the Megawizard.