rams in Quartus

You can instantiate the example altRAMB4_S16_S16 also in Verilog. I skipped the step of creating a wrapper module and instantiated the Megawizard generated module directly instead of original RAMB4_S16_S16. You could omit some unused signals, as the port specific clock and the enables, that I used to be compatible with RAMB4_S16_S16 definition.

altRAMB4_S16_S16 mem (
	.address_a (ADDRA),
	.address_b (ADDRB),
	.clock_a (clk),
	.clock_b (clk),
	.data_a (DINA),
	.data_b (DINB),
	.enable_a (1'b1),
	.enable_b (1'b1),
	.wren_a ( WE),
	.wren_b ( WE),
	.q_a (DOUTA),
	.q_b (DOUTB)
	);