Questions: Intel oneAPI 24.2 with DE10-Agilex and Related Environment setup

Thank you Feng!

Were you able to generate a bitstream using 2024.1 and Quartus® Prime 21.2 by removing other versions?

For what it's worth, I was actually able to generate a bitstream using oneAPI 2024.2 and Quartus® Prime 21.2 on one of our lab machines using a fresh installation. For the record, this was with -DPART=4 in the fpga_compile code sample.

# Set up environment
 $ source /opt/intel/oneapi/2024.2/oneapi-vars.sh --force
 $ export PATH="$PATH:/opt/intel/FPGA_pro/21.2/quartus/bin"
 $ which quartus
/opt/intel/FPGA_pro/21.2/quartus/bin/quartus
 $ cd oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/build_2024.2/
 $ aoc -version
Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline Compiler
Version 2024.2.1 Build 8907061a4a7bb8b03783e9f52adc9762aaf4d91d Pro Edition
Copyright (C) 2024 Intel Corporation
 $ echo $LM_LICENSE_FILE
<...>/license0046.dat

# use CMake to generate build script and build FPGA device image
 $ cmake .. -DPART=4 -DFPGA_DEVICE=de10_agilex:B2E2_8GBx4
-- The CXX compiler identification is Clang 19.0.0
-- Check for working CXX compiler: /opt/intel/oneapi/2024.2/bin/icpx
-- Check for working CXX compiler: /opt/intel/oneapi/2024.2/bin/icpx -- works
-- Detecting CXX compiler ABI info
-- Detecting CXX compiler ABI info - done
-- Detecting CXX compile features
-- Detecting CXX compile features - done
-- Sources file part4_dpcpp_lambda_buffers/src/vector_add.cpp
-- Configuring the design to run on FPGA board de10_agilex:B2E2_8GBx4
-- Additional USER_FPGA_FLAGS=
-- Additional USER_FLAGS=
-- Additional USER_INCLUDE_PATHS=../../../../include
-- Additional USER_LIB_PATHS=
-- Additional USER_LIBS=
-- Configuring done
-- Generating done
-- Build files have been written to: /home/whitepau/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/build_2024.2
 $ time make fpga
[ 33%] To compile manually:
/opt/intel/oneapi/2024.2/bin/icpx -I../../../../../include -fsycl -fintelfpga -Wall -qactypes -DFPGA_HARDWARE -c ../part4_dpcpp_lambda_buffers/src/vector_add.cpp -o CMakeFiles/fpga.dir/part4_dpcpp_lambda_buffers/src/vector_add.cpp.o
To link manually:
/opt/intel/oneapi/2024.2/bin/icpx -fsycl -fintelfpga -qactypes -Xshardware -Xstarget=de10_agilex:B2E2_8GBx4 -reuse-exe=/home/whitepau/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/build_2024.2/vector_add.fpga -o vector_add.fpga CMakeFiles/fpga.dir/part4_dpcpp_lambda_buffers/src/vector_add.cpp.o
[ 33%] Built target displayFPGACompileCommands
[ 66%] Linking CXX executable vector_add.fpga
warning: -reuse-exe file '/home/whitepau/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/build_2024.2/vector_add.fpga' not found; ignored
aoc: Compiling for FPGA. This process may take several hours to complete.  Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets.  If the reports indicate performance targets are not being met, code edits may be required.  Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs.
[100%] Built target fpga
real    139m54.261s
user    358m27.793s
sys     27m7.830s