ClaraIF
New Contributor
New ContributorQuestions about the ALTPLL module in Quartus Prime 20.1 Lite
I would like to raise some issues that have arisen while using Quartus 20.1 Lite and the ALTPLL module:
- How does the Band Width setting affect the PLL lock mechanism? Specifically, if the configuration allows for a wider input clock frequency range, does this imply that the generated output clock could have greater variability? Or is the output frequency always guaranteed to be exactly as configured as long as the input clock remains within the selected BW range?
- Does the BW range affect the deactivation of the Locked signal? In other words, does having a more permissive BW range reduce the probability of Locked being deactivated?
- Does the selected BW range affect the Quartus compiler’s timing analysis? What output clock deviation does the timing analysis take into account when a specific BW setting is applied?
- I wanted to check the compilation results for the PLL with the different BW options. It compiles correctly with both “Low” and “Medium”, but when I select “High” after compilation, it gives me the results for “Medium”. No error appears in "MegaWizard Plug-In Manager"; in fact, the message ‘Able to implement the requested PLL’ appears. Could it be a problem with my PLL configuration? Or with the project configuration itself? Could you clarify how such a change would affect the compiler’s behaviour and timing analysis results? Is there official documentation on the internal operation of the PLL and how the BW affects it? I found the next ones, but I would like to know if there is more: "MAX10 Clocking and PLL User Guide" and "PLL IP Core User Guide".
Thank you,
Clara Iracheta
