Forum Discussion
ClaraIF
New Contributor
New ContributorQuestions about the ALTPLL module in Quartus Prime 20.1 Lite
I would like to raise some issues that have arisen while using Quartus 20.1 Lite and the ALTPLL module: How does the Band Width setting affect the PLL lock mechanism? Specifically, if the configur...
ClaraIFNew Contributor
New ContributorHi Sheng.
Thank you for your reply!
The question arises because we have observed noise issues in the clock during some tests and we want to maximise the availability of the equipment without compromising security (ensuring that the time analysis is correct for the effective PLL output frequency). In other words, we want the noise/jitter to have as little effect as possible and only lose the Locked status when the output frequency is compromised.
Which configuration is more appropriate: Low or High bandwidth?
Thank you,
Clara
