Questions about the ALTPLL module in Quartus Prime 20.1 Lite

Hi,

How does the Band Width setting affect the PLL lock mechanism?

May check here https://www.intel.com/content/www/us/en/docs/programmable/683732/17-0/parameter-settings-89007.html

Specifically, if the configuration allows for a wider input clock frequency range, does this imply that the generated output clock could have greater variability?

Not exactly. The frequency ratio is still enforced.

Or is the output frequency always guaranteed to be exactly as configured as long as the input clock remains within the selected BW range?

Yes, the output frequency is always guaranteed to be exactly as configured, as long as the PLL is locked and the input clock frequency is within the allowable operating range (which includes the effect of the bandwidth setting and VCO range).

Does the BW range affect the deactivation of the Locked signal? In other words, does having a more permissive BW range reduce the probability of Locked being deactivated?

Yes. Can refer here https://www.intel.com/content/www/us/en/docs/programmable/683732/17-0/parameter-settings-89007.html also

Does the selected BW range affect the Quartus compiler’s timing analysis? What output clock deviation does the timing analysis take into account when a specific BW setting is applied?

Not exactly.

but when I select “High” after compilation, it gives me the results for “Medium”.

This is reporting bug, will report this. You can rest assured that the configuration is taking place correctly if you refer to the bandwidth range which is correct.

Thanks,

Regards,

Sheng