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ClaraIF's avatar
ClaraIF
Icon for New Contributor rankNew Contributor
3 months ago

Questions about the ALTPLL module in Quartus Prime 20.1 Lite

I would like to raise some issues that have arisen while using Quartus 20.1 Lite and the ALTPLL module: How does the Band Width setting affect the PLL lock mechanism? Specifically, if the configur...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 months ago
Hi,
PLL bandwidth settings affects dynamic behaviour, ability to track a frequency modulated or jittering clock and locking speed. It does not affect static locking and pulling frequency range as far as I'm aware.

PLL output in locked state follows the defined frequency ratio.

Timing analysis and compilation result doesn't depend on bandwidth setting.