Forum Discussion
ClaraIF
New Contributor
New ContributorQuestions about the ALTPLL module in Quartus Prime 20.1 Lite
I would like to raise some issues that have arisen while using Quartus 20.1 Lite and the ALTPLL module: How does the Band Width setting affect the PLL lock mechanism? Specifically, if the configur...
FvM
Super Contributor
Super ContributorHi,
PLL bandwidth settings affects dynamic behaviour, ability to track a frequency modulated or jittering clock and locking speed. It does not affect static locking and pulling frequency range as far as I'm aware.
PLL output in locked state follows the defined frequency ratio.
Timing analysis and compilation result doesn't depend on bandwidth setting.
PLL bandwidth settings affects dynamic behaviour, ability to track a frequency modulated or jittering clock and locking speed. It does not affect static locking and pulling frequency range as far as I'm aware.
PLL output in locked state follows the defined frequency ratio.
Timing analysis and compilation result doesn't depend on bandwidth setting.
