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DeadEnd's avatar
DeadEnd
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1 year ago
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Question Regarding Clock Synchronization in EyeQ BER function

Hello, I have a question regarding Stratix.

I am looking to measure BER using the EyeQ feature on Stratix. Here’s my question: when Stratix transmits and receives data for BER measurement, it synchronizes with the clock.

Does this synchronization only occur at the clock's rising edge? Or does it not synchronize at the falling edge, similar to DDR?

Additionally, is there a feature in Qsys, IP, or Quartus that enables operation like DDR? I've been searching but can't find any information, so I'm asking here.

Please note that I am using Stratics V and my Quartus version is 14.0.

Thank you for your help!

Hdl
Platform
  • Kshitij_Intel's avatar
    Kshitij_Intel
    1 year ago

    Hi,

    ​

    I understand, your confusion. My understanding is that from the statement i.e., "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS." it is Single Data Rate Only but width of data and control word becomes double i.e., 64-bit and 8-bit Actually you achieves the same data rate.


    So, no need to sample at rising and falling edge for double data rate.


    Hope this clarifies.


    Thank you,

    Kshitij Goel


7 Replies

    • DeadEnd's avatar
      DeadEnd
      Icon for New Contributor rankNew Contributor
      1 year ago

      Thank you for your reply.

      But the contents you shared show that "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS."

      Since BER uses transicever, doesn't that mean DDR is not supported?

      If not, I would be very grateful if you could tell me how to determine which protocol I used.

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,

    ​

    I understand, your confusion. My understanding is that from the statement i.e., "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS." it is Single Data Rate Only but width of data and control word becomes double i.e., 64-bit and 8-bit Actually you achieves the same data rate.


    So, no need to sample at rising and falling edge for double data rate.


    Hope this clarifies.


    Thank you,

    Kshitij Goel


  • DeadEnd's avatar
    DeadEnd
    Icon for New Contributor rankNew Contributor
    1 year ago

    Oh, so the transceiver can get the effect of DDR with just SDR with width of data and control word?
    And if so, it sends 64 bits of data in one clock, right?

    So does Tranceiver always send 64 bits of data in one clock?

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

    Thank you,

    Kshitij Goel


    • DeadEnd's avatar
      DeadEnd
      Icon for New Contributor rankNew Contributor
      1 year ago

      I apologize for the delay in responding.

      I'll do some more research and ask you if you have any additional questions.
      Thank you very much for your help.