Forum Discussion
Question Regarding Clock Synchronization in EyeQ BER function
- 2 years ago
Hi,
I understand, your confusion. My understanding is that from the statement i.e., "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS." it is Single Data Rate Only but width of data and control word becomes double i.e., 64-bit and 8-bit Actually you achieves the same data rate.
So, no need to sample at rising and falling edge for double data rate.
Hope this clarifies.
Thank you,
Kshitij Goel
Hi,
And if so, it sends 64 bits of data in one clock, right?
--> Yes.
So, does Transceiver always send 64 bits of data in one clock?
--> No, it depends on which protocol you are using. Always refer UG 4.2.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and... (intel.com)
Regards,
Kshitij Goel