Forum Discussion
Question Regarding Clock Synchronization in EyeQ BER function
- 2 years ago
Hi,
I understand, your confusion. My understanding is that from the statement i.e., "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS." it is Single Data Rate Only but width of data and control word becomes double i.e., 64-bit and 8-bit Actually you achieves the same data rate.
So, no need to sample at rising and falling edge for double data rate.
Hope this clarifies.
Thank you,
Kshitij Goel
Hi,
It depends on the which protocol you are implementing. Please refer 4.2.2. 10GBASE-R and 10GBASE-KR Supported Features (intel.com) For this protocol it supports DDR mode.
Thank you,
Kshitij Goel
- DeadEnd2 years ago
New Contributor
Thank you for your reply.
But the contents you shared show that "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS."
Since BER uses transicever, doesn't that mean DDR is not supported?
If not, I would be very grateful if you could tell me how to determine which protocol I used.