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DimitrisGrn's avatar
DimitrisGrn
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1 year ago

Question about M20K block packing

I am using Intel Quartus Prime 21.1, targeting the Stratix 10 MX 2100 device. I have several read/write avalon memory-mapped interfaces from a Load/Store unit that are connected to True Dual-Port RA...
Compilation
Hdl
Shuo_Zhang's avatar
Shuo_Zhang
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1 year ago

Hi,

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When the software implements the RAM instances on the M20Ks, it will merge several instances to one M20K when one RAM instance does not fully occupy one M20K block. But things going to be different when you enable the different pipeline registers because the port and port register resource on one M20K is limited. If the port number and the port register number on one M20K are insufficient to support the combinational implementation of several RAM instances, the software will split the RAM instances into different M20K blocks.

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If the M20K is not enough, please consider using the MLAB resource. When both the M20K and MLAB resources are exhausted, it would be hard to close timing, at that case, please consider reducing the scale of your design.


Best Regards,

Shuo